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ltc 4354 1 4354fc typical a pplica t ion fea t ures descrip t ion negative voltage diode-or controller and monitor the lt c ? 4354 is a negative voltage diode-or controller that drives two external n-channel mosfets. it replaces two schottky diodes and the associated heat sink, saving power and area. the power dissipation is greatly reduced by using n-channel mosfets as the pass transistors. power sources can easily be ored together to increase total system power and reliability. when first powered up, the mosfet body diode conducts the load current until the pass transistor is turned on. the ltc4354 servos the voltage drop across the pass transistors to ensure smooth transfer of current from one transistor to the other without oscillation. the mosfets are turned off in less than 1 s whenever the corresponding power source fails or is shorted. fast turn-off prevents the reverse current from reaching a level that could damage the pass transistors. a fault detection circuit with an open-drain output capable of driving an led or opto-coupler indicates either mosfet short, mosfet open or supply failed. C48v diode-or power dissipation vs load current a pplica t ions n controls n-channel mosfets n replaces power schottky diodes n less than 1s turn-off time limits peak fault current n 80v operation n smooth switchover without oscillation n no reverse dc current n fault output n selectable fault thresholds n available in 8-lead (3mm 2mm) dfn and 8-lead so packages n advancedtca systems n C48v distributed power systems n computer systems/servers n telecom infrastructure n optical networks l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and hot swap, powerpath and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. ltc4354 load db ga da gb v ss v b = ?48v v a = ?48v ?48v_rtn fault irf3710 irf3710 4354 ta01 v cc 33k 12k 2k 2k led 1f current (a) 0 0 power dissipation (w) 1 2 3 4 6 5 2 4 6 4354 ta01b 8 10 diode (mbr10100) fet (irf3710) power saved
ltc 4354 2 4354fc lead free finish tape and reel (mini) tape and reel part marking* package description temperature range ltc4354cddb#trmpbf ltc4354cddb#trpbf lbbk 8-lead (3mm 2mm) plastic dfn 0c to 70c ltc4354iddb#trmpbf ltc4354iddb#trpbf lbmb 8-lead (3mm 2mm) plastic dfn C40c to 85c trm = 500 pieces. *temperature grades are identified by a label on the shipping container. a bsolu t e maxi m u m r a t ings i cc (100 s duration ) ............................................... 50 ma o utput voltages ga , gb ......................................... C 0.3 v to v cc + 0.3 v fault ...................................................... C 0.3 v to 7v input voltages da , db ................................................... C 0.3 v to 80 v input current da , db current ................................... C1 ma to 20 ma (note 1) o r d er i n f or m a t ion lead free finish tape and reel part marking package description temperature range ltc4354cs8#pbf ltc4354cs8#trpbf 4354 8-lead plastic so 0c to 70c ltc4354is8#pbf ltc4354is8#trpbf 4354i 8-lead plastic so C40c to 85c consult lt c marketing for parts specified with wider operating temperature ranges. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ top view 9 ddb package 8-lead (3mm 2mm) plastic dfn 5 6 7 8 4 3 2 1da v ss v cc ga db fault gb v ss t jmax = 125c, ja = 76c/w exposed pad (pin 9) is v ss , connection to pcb optional 1 2 3 4 8 7 6 5 top view db fault gb v ss da v ss v cc ga s8 package 8-lead plastic so t jmax = 125c, ja = 150c/w operating temperature range ltc 4 354 c ................................................ 0 c to 70 c ltc 4 354 i ............................................. C 40 c to 85 c storage temperature range .................. C 65 c to 150 c lead temperature ( soldering , 10 sec ) ................... 30 0 c p in c on f igura t ion
ltc 4354 3 4354fc the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. i cc = 5ma, v ss = 0v, unless otherwise noted. e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: i cc is defined as the current level where the v cc voltage is lower by 100mv from the value with 2ma of current. symbol parameter conditions min typ max units v z internal shunt regulator voltage i cc = 5ma l 10.25 11 11.75 v ?v z internal shunt regulator load regulation i cc = 2ma to 10ma 200 300 mv v cc operating voltage range l 4.5 v z v i cc v cc supply current v cc = (v z C 0.1v), note 2 v cc = 5v l l 0.5 1.2 0.8 2 1.1 ma ma v gate gate pins output high voltage v cc = 10.25v v cc = 5v 10 4.75 10.25 v v i gate gate pins pull-up current v sd = 60mv; v gate = 5.5v v sd = 0v; v gate = 5.5v C15 15 C30 30 C60 60 a a ?v sd source drain sense threshold voltage (v ss C v dx ) l 10 30 55 mv ?v sd( f lt ) source drain fault detection threshold (v ss C v dx ); v cc = 7v to v z l 200 260 320 mv t off gate turn-off time in fault condition c gate = 3300pf; v gate 2v; v sd = C0.4v 0.7 1.2 s v fault fault pin output low i fault = 5ma l 200 400 mv i fault fault pin leakage current v fault = 5v l 1 a i d drain pin input current v dx = 0v v dx = 80v C3.5 1.1 C2.5 1.5 C1.5 1.9 a ma note 3: an internal shunt regulator limits the v cc pin to less than 12v above v ss . driving this pin to voltages beyond the clamp may damage the part. note 4: all currents into pins are positive ; all voltages are referenced to v ss unless otherwise specified.
ltc 4354 4 4354fc specifications are at t a = 25c , i cc = 5ma, v ss = 0 v, unless otherwise noted. typical p er f or m ance c harac t eris t ics source drain sense voltage vs temperature i gate(up) vs ?v sd gate turn-off time vs temperature fault threshold voltage vs temperature drain pin current vs temperature drain pin current vs voltage shunt regulator voltage vs input current shunt regulator voltage vs input current at temperature source drain sense voltage vs supply voltage i cc (ma) 0 v z (v) 11.0 20 4354 g01 10.0 11.5 10.5 10 5 15 12.0 temperature (c) ?50 v z (v) 11.4 11.0 10.6 11.2 10.8 ?25 0 25 4354 g02 50 75 100 125 i cc = 10ma i cc = 5ma i cc = 2ma v cc (v) 5 20 ?v sd (mv) 30 25 35 7 9 11 12 4354 g03 40 6 8 10 temperature (c) ?50 v sd (mv) 40 30 20 35 25 ?25 0 25 4354 g04 50 75 100 125 ?v sd (mv) 30 i gate(up) (a) 100 40 60 0 80 20 40 50 60 4354 g05 70 80 90 temperature (c) ?50 t off (ns) 740 700 660 720 680 ?25 0 25 4354 g05 50 75 100 125 temperature (c) ?50 ?v sd(flt) (mv) 290 250 210 270 230 ?25 0 25 4354 g06 50 75 100 125 temperature (c) ?50 i d (a) ?3.2 ?2.8 ?2.4 ?3.0 ?2.6 ?25 0 25 4354 g08 50 75 100 125 v dx = 0v v dx (v) 0.3 i d (ma) ?1 ?0.5 ?0.75 ?0.25 0 0.4 0.5 0.6 4354 g09 0.7 0.8 0.9 1 90c 25c ?45c
ltc 4354 5 4354fc p in func t ions da, db (pins 1, 8): drain voltage sense inputs. these pins sense source drain voltage drop across the n-channel mosfets. an external resistor is recommended to pro- tect these pins from transient voltages exceeding 80 v in extreme fault conditions. for kelvin sensing, connect these pins as close to the drains as possible. connect to v ss if unused. v cc (pin 3): positive supply voltage input. connect this pin to the positive side of the supply through a resistor. an internal shunt regulator that can sink up to 20ma typically clamps v cc at 11 v. bypass this pin with a 1f capacitor to v ss . ga, gb (pins 4, 6): gate drive outputs. gate pins pull high to 10 v minimum, fully enhancing the n-channel mosfet, when the load current creates more than 30 mv of drop across the mosfet. when the load current is small, the gates are actively servoed to maintain a 30 mv drop across the mosfet. if reverse current develops more than C140mv of voltage drop across the mosfet, the pins pull low to v ss in less than 1 s. quickly turning off the pass transistors prevents excessive reverse currents. leave the pins open if unused. v ss (pins 2, 5): negative supply voltage input. this is the device negative supply input and connects to the common source connection of the n-channel mosfets. it also connects to the source voltage sense input of the servo amplifiers. for kelvin sensing, connect pin 5 as close to the common source terminal of the mosfets as possible. fault ( pin 7): fault output. open - drain output that normally pulls the fault pin to v ss and shunts current to turn off an external led or opto-coupler. in the fault condition, where the pass transistor is fully on and the voltage drop across it is higher than the fault threshold, the fault pin goes high impedance, turning on the led or opto-coupler. this indicates that one or both of the pass transistors have failed open or failed short creating a cross conduction current in between the two power supplies. connect to v ss if unused. exposed pad (pin 9): exposed pad is common to v ss and may be left open or connected to pins 2 and 5. func t ional diagra m db gb da ga 30mv bv = 11v 30mv v ss v cc v ss v ss 55k 4354 fd v ss fault ? + ? + + ? + ? fault detection amp b amp a 5 4 1 6 8 2 7 3 v ss 55k
ltc 4354 6 4354fc ti m ing diagra m high availability systems often employ parallel-connected power supplies or battery feeds to achieve redundancy and enhance system reliability. oring diodes have been a popular means of connecting these supplies at the point-of-load. the disadvantage of this approach is the significant forward-voltage drop and resulting efficiency loss. this drop reduces the available supply voltage and dissipates significant power. a desirable circuit would behave like diodes but without the voltage drop and the resulting power dissipation. the ltc4354 is a negative voltage diode- or controller that drives two external n-channel mosfets as pass transis- tors to replace oring diodes. the mosfets are connected together at the source pins. the common source node is connected to the v ss pin which is the negative supply of the device. it is also connected to the positive inputs of the amplifiers that control the gates to regulate the volt- age drop across the pass transistors. using n-channel mosfets to replace schottky diodes reduces the power dissipation and eliminates the need for costly heat sinks or large thermal layouts in high power applications. at power-up, the initial load current flows through the body diode of the mosfet and returns to the supply with the lower terminal voltage. the associated gate pin will immediately start ramping up and turn on the mosfet. the amplifier tries to regulate the voltage drop between the source and drain connections to 30 mv. if the load current causes more than 30 mv of drop, the gate rises to further enhance the mosfet. eventually the mosfet 4354 td01 v ss ? v dx v gate t off 100mv 2v ?400mv o pera t ion gate is driven fully on and the voltage drop is equal to the r ds(on) ? i load . when the power supply voltages are nearly equal, this regulation technique ensures that the load current is smoothly shared between them without oscillation. the current level flowing through each pass transistor depends on the r ds(on) of the mosfet and the output impedance of the supplies. in the case of supply failure, such as if the supply that is conducting most or all of the current is shorted to the return side, a large reverse current starts flowing through the mosfet that is on, from any load capacitance and through the body diode of the other mosfet, to the sec- ond supply. the ltc4354 detects this failure condition as soon as it appears and turns off the mosfet in less than 1s. this fast turn-off prevents the reverse current from ramping up to a damaging level. in the case where the pass transistor is fully on but the voltage drop across it exceeds the fault threshold, the fault pin goes high impedance. this allows an led or opto-coupler to turn on indicating that one or both of the pass transistors have failed. the ltc4354 is powered from system ground through a current limiting resistor. an internal shunt regulator that can sink up to 20 ma clamps the v cc pin to 11 v above v ss . a 1 f bypass capacitor across v cc and v ss pins filters supply transients and supplies ac current to the device.
ltc 4354 7 4354fc input power supply the power supply for the device is derived from C48_ rtn through an external current limiting resistor ( r in ). an internal shunt regulator clamps the voltage at v cc pin to 11v. a 1 f decoupling capacitor to v ss is recommended. it also provides a soft-start to the part. r in should be chosen to accommodate the maximum supply current requirement of 2 ma at the expected input operating voltage. r in (v in(min) ? v z(max) ) i cc(max) the power dissipation of the resistor is calculated at the maximum dc input voltage: p = (v in(max) ? v cc(min) ) 2 r in if the power dissipation is too high for a single resistor, use multiple low power resistors in series instead of a single high power component. m osfet s election the ltc4354 drives n-channel mosfets to conduct the load current. the important features of the mosfets are on - resistance r ds ( on ) , the maximum drain - source voltage v dss , and the threshold voltage. the gate drive for the mosfet is guaranteed to be more than 10 v and less than 12v . this allows the use of standard threshold voltage n-channel mosfets. an external zener diode can be used to clamp the potential at the v cc pin to as low as 4.5 v if the gate to source rated breakdown voltage is less than 12v. the maximum allowable drain-source voltage, v (br)dss, must be higher than the supply voltages. if the inputs are shorted, the full supply voltage will appear across the mosfets. a pplica t ions i n f or m a t ion figure 1. method of protecting the da and db pins from negative inputs. one channel shown the ltc4354 tries to servo the voltage drop across the mosfet to 30 mv in the forward direction by controlling the gate voltage and sends out a fault signal when the voltage drop exceeds the 260 mv fault threshold. the r ds(on) should be small enough to conduct the maximum load current while not triggering a fault, and to stay within the mosfets power rating at the maximum load current (i 2 ? r ds(on) ). fault conditions ltc4354 monitors fault conditions and turns on an led or opto-coupler to indicate a fault. when the voltage drop across the pass transistor is higher than the 260 mv fault threshold, the internal pull-down at the fault pin turns off and allows the current to flow through the led or opto- coupler. conditions that cause high voltage across the pass transistor include: short in the load circuitry, excessive load current, fet open while conducting current, and fet short on the channel with the higher supply voltage. the fault threshold is internally set to 260mv. in the event of fet open on the channel with the more negative supply voltage, if the voltage difference is high enough, the substrate diode on the da or db pins will forward bias. the current flowing out of the pins must be limited to a safe level (<1 ma) to prevent device latch up. schottky diodes can be used to clamp the voltage at the da and db pins, as shown in figure 1. 4354 f01 da ga ltc4354 v ss mmbd2836lt1 1k 1k
ltc 4354 8 4354fc ltc4354 to module input db ga da gb v ss v b v a ?48v_rtn fault m2 irf3710s m1 irf3710s 4354 f02 v cc r3 33k r in 12k 0.5w d1 led 1 8 4 3 6 2, 5 7 r1 2k r2 2k c in 1f a pplica t ions i n f or m a t ion system power supply failure ltc4354 automatically supplies load current from the system supply with the more negative input potential. if this supply is shorted to the return side, a large reverse current flows from its pass transistor. when this reverse current creates C140 mv of voltage drop across the drain and source pins of the pass transistor, the ltc4354 drives the gate low fast and turns it off. the remaining system power supply will deliver the load current through the body diode of its pass transistor until the channel turns on. the ltc4354 ramps the gate up and turns on the n-channel mosfet to reduce the voltage drop across it, a process that takes less than 1 ms depending on the gate charge of the mosfet. drain resistor tw o resistors are required to protect the da and db pins from transient voltages higher than 80 v. in the case when the supply with the lower potential is shorted to the return side due to supply failure, a reverse current flows briefly through the pass transistor to the other supply to discharge the output capacitor. this current stores energy in the stray inductance along the current path. once the pass transistor is turned off, this energy forces the drain terminal of the fet high until it reaches the breakdown voltage. if this voltage is higher than 80 v, the internal esd devices at the da and db pins might break down and become damaged. the external drain resistors limit the current into the pins and protect the esd devices. a 2k resistor is recommended for 48 v applications. larger resistor values increase the source drain sense threshold voltage due to the input current at the drain pins. loop stability the servo loop is compensated by the parasitic capacitance of the power n- channel mosfet. no further compensation components are normally required. in the case when a mosfet with very small parasitic capacitance is chosen, a 1000 pf compensation capacitor connected across the gate and source pins might be required. design example the following demonstrates the calculations involved for selecting components in a C36 v to C72 v system with 5a maximum load current, see figure 2. first, select the input dropping resistor. the resistor should allow 2ma of current with the supply at C36v. r in (36v ? 11.5v) 2ma = 12.25k the nearest lower 5% value is 12k. figure 2. C36v to C72v/5a design example
ltc 4354 9 4354fc a pplica t ions i n f or m a t ion typical a pplica t ions C5.2v diode-or controller positive low voltage diode-or combines multiple switching converters the worst-case power dissipation in r in : p = (72v ? 10.5v) 2 12k = 0.315w choose a 12k 0.5 w resistor or use two 5.6k 0.25 w resis- tors in series. next, choose the n- channel mosfet. the 100 v , irf3710 s in dd-pak package with r ds(on) = 23m ( max) offers a good solution. the maximum voltage drop across it is: ? v = (5a)(23m) = 115mv the maximum power dissipation in the mosfet is a mere: p = (5a)(115mv) = 0.6w r1 and r2 are chosen to be 2 k to protect da and db pins from being damaged by high voltage spikes that can occur during an input supply fault. the led, d1, requires at least 1 ma of current to fully turn on, therefore r3 is set to 33 k to accommodate lowest input supply voltage of C36v. layout considerations the following advice should be considered when laying out a printed circuit board for the ltc4354. the bypass capacitor provides ac current to the device so place it as close to the v cc and v ss pins as possible. the inputs to the servo amplifiers, da, db and v ss pins, should be connected directly to the mosfets terminals using kelvin connections for good accuracy. keep the traces to the mosfets wide and short. the pcb traces associated with the power path through the mosfets should have low resistance. ltc4354 load db ga da gb v ss v b = ?5.2v v a = ?5.2v gnd fault m2 si4466dy m1 si4466dy 4354 ta02 v cc r3 2k d1 led c in 1f 2, 5 6 1 48 3 7 12v 470 240* 1.2v, 200a output bus 4354 ta03 *optional preload hat2165 6 hat2165 6 1.2v 100a input 1f v ee ga,gb v cc ltc4354 da,db 12v 470 240* 1.2v 100a input 1f v ee ga,gb v cc ltc4354 da,db
ltc 4354 10 4354fc C36v to C72v/20a high current with parallel fets C12v diode-or controller typical a pplica t ions 3 ltc4354 db ga da gb v ss v b = ?48v fault m4 irf3710 m3 irf3710 4354 ta04 v cc 3 r6 30k r in2 10k r5 2k r4 2k d2 led c in2 1f ltc4354 db ga da gb v ss v a = ?48v ?48v out ?48v_rtn rtn rtn fault m2 irf3710 m1 irf3710 v cc r3 30k r in1 10k r2 2k r1 2k d1 led c in1 1f 2, 5 6 1 48 7 2, 5 6 1 48 7 ltc4354 load db ga da gb v ss 2, 5 6 1 48 v b = ?12v v a = ?12v gnd fault m2 si4862dy 3 7 m1 si4862dy 4354 ta05 v cc r3 10k r in 2k in754 bv = 6.8v c in 1f d1 led d z
ltc 4354 11 4354fc p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 2.00 0.10 (2 sides) note: 1. drawing conforms to version (wecd-1) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 0.56 0.05 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.05 typ 2.15 0.05 (2 sides) 3.00 0.10 (2 sides) 1 4 8 5 pin 1 bar top mark (see note 6) 0.200 ref 0 ? 0.05 (ddb8) dfn 0905 rev b 0.25 0.05 0.50 bsc pin 1 r = 0.20 or 0.25 45 chamfer 0.25 0.05 2.20 0.05 (2 sides) recommended solder pad pitch and dimensions 0.61 0.05 (2 sides) 1.15 0.05 0.70 0.05 2.55 0.05 package outline 0.50 bsc ddb package 8-lead plastic dfn (3mm 2mm) (reference ltc dwg # 05-08-1702 rev b)
ltc 4354 12 4354fc p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. .016 ? .050 (0.406 ? 1.270) .010 ? .020 (0.254 ? 0.508) 45 0? 8 typ .008 ? .010 (0.203 ? 0.254) so8 0303 .053 ? .069 (1.346 ? 1.752) .014 ? .019 (0.355 ? 0.483) typ .004 ? .010 (0.101 ? 0.254) .050 (1.270) bsc 1 2 3 4 .150 ? .157 (3.810 ? 3.988) note 3 8 7 6 5 .189 ? .197 (4.801 ? 5.004) note 3 .228 ? .244 (5.791 ? 6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610)
ltc 4354 13 4354fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number c 04/12 updated package/order information format 2 changed figure 2 8 updated ddb package drawing 11 (revision history begins at rev c)
ltc 4354 14 4354fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2004 lt 0412 rev c ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments lt ? 1640ah/lt1640al negative high voltage hot swap? controllers in so-8 negative high voltage supplies from C10v to C80v lt4250 C48v hot swap controller active current limiting, supplies from C20v to C80v ltc4251/ltc4251-1/ ltc4251-1 C48v hot swap controllers in sot-23 fast active current limiting, supplies from C15v ltc4252-1/ltc4252-2/ ltc4252-1a/ltc4252-2a C48v hot swap controllers in ms8/ms10 fast active current limiting, supplies from C15v, drain accelerated response ltc4253 C48v hot swap controller with sequencer fast active current limiting, supplies from C15v, drain accelerated response, sequenced power good outputs lt4351 mosfet diode-or controller n-channel mosfet, 1.2v to 18v, fast switching for high current ltc4412 low loss powerpath? controller in thinsot ? p-channel mosfet, 3v to 28v range ltc4354 load db ga da gb v ss v b = ?48v v a = ?48v ?48v_rtn fault irf540ns irf540ns 4354 ta06 v cc 33k 12k 0.5w 1k 1k 1k 1k led 1f mmbd2836lt1 mmbd2836lt1 C48v diode-or controller with fuse monitoring

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